This invention is in the field of data processing and, in particular, relates to a method and apparatus for the resolution of memory access demands in multiple processor systems.
In many advanced data processing systems, a number of independent processors can have access to a main memory shared by the system. When a processor wishes only to read a particular memory location or even rewrite a specified location, access can be controlled sequentially with little cost in performance. However, it is also common for processors to perform an operation known as a read-modify-write (RMW) operation or the like. This operation involves reading data out of a selected memory location, processing the data read out, and writing modified data back into the specified location.
The conventional method for protecting the system from situations in which a second processor seeks access to a location in the middle of a RMW operation has been to freeze the memory bus until the operation is completed; this solution, unfortunately, cuts drastically into performance. In response, systems also have been proposed that use flags, lock bits or the like to deactivate a block of data being manipulated. Nonetheless, a problem remains because when one processor is operating on such locked data, another processor often cannot read the data much less operate upon it concurrently.
The problem of handling multiple access requests can become acute when one of the independent processors is carrying out instructions on a string of data, such as moving a string of ASCII-coded data. Since the 8-bit ASCII words (representing language characters, punctuation, etc.) are smaller than the typical 16 bit (or 32 bit) registers around which advanced systems are designed, a modification which involves changing less than the full 16 (or 32) bits often is not controlled by the system hardware.
For example, a 32-bit wide memory register common to a number of processors can store two data blocks consisting of an integer value (i.e., a fortran *2 integer) on one side (the upper 16 bits) and two ASCII characters on the other side (the lower 16 bits). If a first processor wished to replace the ASCII characters only, it would need to read the entire register, modify the contents to keep the integer value on one side while changing the characters on the other side and then write the modified 32-bits into the memory. Since this RMW operation cannot occur instantaneously, a second processor might write a new entry into part of the register in the interim (i.e., to replace the integer value) and this data would be lost if the first processor was allowed to enter its modification without any controls. Hence, the solution to date has been to exclude the second processor in one fashion or another while the first processor performs a RMW operation.
There exists a need for better memory access systems in which a plurality of processors can share memory locations with a minimum of interruptions. In particular, a long-felt need would be satisfied by an access scheme which would permit other processors to perform RMW operations without freezing the memory bus or completely deactivating a block of data.